Field of the Invention
The invention relates to a method for calibrating a test apparatus for testing a number of electronic components in parallel, in particular semiconductor memories, to a time-critical parameter. In the method, the components are positioned in batches at predetermined test positions and the parameter is measured. The various test positions give different measurement results since they are not identical and because of the different wiring to the measurement unit for measuring the parameter. These different measurement results are compensated for on the basis of forming mean values of the parameter measurements at all of the test positions.
For purposes of the present document, the expression xe2x80x9ctesting a modulexe2x80x9d means the analysis of the module with respect to a specific time-critical value in order to make a decision xe2x80x9ctest passedxe2x80x9d or xe2x80x9cpassxe2x80x9d, or xe2x80x9ctest failedxe2x80x9d or xe2x80x9cfailxe2x80x9d. In this case, the timing accuracy, the so-called OTA (Overall Timing Accuracy) of a test apparatus governs the accuracy limit to which the module, for example an SGRAM, can be qualified. The time parameters to be checked require a test system accuracy which is better than that of the time parameters to be checked by a factor of 4 to 6. Previous test apparatuses are not directly suitable for the currently existing requirements in conjunction with semiconductor memory modules, such as the SGRA 32M and 128M, since this apparatus does not ensure the abovementioned factor of 4 to 6. In principle this problem can be overcome by using of test apparatuses that provide the necessary accuracy. However, this has the disadvantage that previous test apparatuses, procured at high cost, must be replaced by new apparatuses whose measurement accuracy is better. Issued German Patent DE 199 39 595 C1 discloses a test arrangement for a large number of semiconductor circuits, in which the test signals have a specific time relationship with the system clock. In this case, the test signals are synchronized by a circuit device in the form of a semiconductor circuit.
It is accordingly an object of the invention to provide a test apparatus for measuring a time-critical parameter and a method for calibrating such a test apparatus which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for calibrating a test apparatus for measuring a time-critical parameter for electronic components. The method includes steps of: providing a test apparatus including test positions for holding the electronic components in batches and a measurement unit to which the test positions are individually connected, the test positions having individual characteristics upon which the time-critical parameter is dependent; for each respective one of the test positions, measuring the time-critical parameter for a number of the electronic components that are temporally successively configured at the respective one of the test positions; determining a position-specific mean value for the time-critical parameter for each respective one of the test positions from measured values corresponding to the respective one of the test positions; determining a position-independent mean value for the time-critical parameter from measured values corresponding to a number of the test positions; for each one of the test positions, determining a difference between the position-specific mean value for the one of the test positions and the position-independent mean value of the time-critical parameter in order to determine an individual offset for the one of the test positions; forming a correction value for each one of the test positions from the offset of the one of the test positions; and calibrating the measurement unit using the correction value for the test positions to reduce the offset of the test positions.
In accordance with an added feature of the invention, the correction value is iteratively formed.
In accordance with an additional feature of the invention, the correction value is iteratively formed using a clock cycle that is dependent on a clock cycle of the batches.
In accordance with another feature of the invention, the correction value is formed after each batch change.
In accordance with a further feature of the invention, the electronic components are provided as semiconductor memories.
One object of the present invention is to provide a method as mentioned initially, which allows time parameters for components, in particular semiconductor memories, to be tested reliably, without having to replace previous test apparatuses by expensive, new, more accurate test apparatuses. A further object of the invention is to provide a test apparatus for carrying out the method.
In other words, the method according to the invention improves the accuracy limits of the test apparatus in the region of the so-called skew error (skew error relates to the time difference between a number of signals with respect to a specific flank, resulting from different delay times). This has the immediate advantage that previous test apparatuses can still be used, and do not need to be replaced by new ones.
In other words, the limits of previous test apparatuses in terms of the timing and calibration are extended by using a statistical method. Indeed, a component that will be tested is measured using a known best-possible time parameter, by using a search algorithm, within the accuracy limits of the test apparatus. The measurement result that is achieved using the method is based on statistically sufficient samples in order, by using mathematically known density functions, for example the Gaussian function, to improve the limit resulting from the intrinsic bandwidth of previous test apparatuses. The method allows individual test apparatus channels, or even groups of test apparatus channels, which are also referred to as test positions in this document, to be improved by factors of two or more with regard to the timing (skew).
A further advantage is that the method is not restricted to being used with a specific test apparatus, but can be used universally. The only precondition for using the method is knowledge of the calibration system for the respective test apparatus, and of the timing on the module to be measured.
In detail, the method provides, in each test position, for a position-specific mean value to be formed from batch parameter measurements, for a position-independent mean value of the batch parameter measurements to be formed at all of the test positions, and for a corrected mean value to be obtained for each test position by adding the difference between the position-specific mean value and the position-independent mean value to the position-specific mean value.
According to the invention, the position-dependent mean value of the parameter measurements is not just matched once, but by successive approximation using a progressive measurement procedure in order to improve the measurement accuracy successively. In this case, the invention provides, in particular, for the use of corrected mean values for the formation process to be updated as a function of the clock cycle of the batches. The updating clock cycle in this case preferably corresponds to the batch clock cycle.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a test apparatus for parallel testing of a number of electronic components, and a method for calibration of the test apparatus, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.